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-- Company: 
-- Engineer: 
-- 
-- Create Date: 27.02.2025 16:25:47
-- Design Name: 
-- Module Name: Wallace - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity wallace is
    Port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
           B : in  STD_LOGIC_VECTOR (7 downto 0);
           P : out  STD_LOGIC_VECTOR (15 downto 0));
end wallace;
 
architecture Behavioral of wallace is
 
component Full_Addar is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
         Cin : in  STD_LOGIC;
          S  : out  STD_LOGIC;
       Cout : out  STD_LOGIC);
end component;
 
component Halfaddar is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           S : out STD_LOGIC;
        Cout : out STD_LOGIC);
end component;
 
 
signal S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34,S35,S36,S37,S38,S39,S40,S41,S42,S43,S44,S45,S46,S47,S48: std_logic;
signal C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C12,C13,C14,C15,C16,C17,C18,C19,C20,C21,C22,C23,C24,C25,C26,C27,C28,C29,C30,C31,C32,C33,C34,C35,C36,C37,C38,C39,C40,C41,C42,C43,C44,C45,C46,C47,C48,C49,C50,C51,C52,C53,C54,C55: std_logic;
 
signal A1B0 : std_logic;
signal A2B0 : std_logic;
signal A3B0 : std_logic;
signal A4B0 : std_logic;
signal A5B0 : std_logic; 
signal A6B0 : std_logic;
signal A7B0 : std_logic;

signal A0B1 : std_logic;
signal A1B1 : std_logic;
signal A2B1 : std_logic;
signal A3B1 : std_logic;
signal A4B1 : std_logic;
signal A5B1 : std_logic; 
signal A6B1 : std_logic;
signal A7B1 : std_logic;

signal A0B2 : std_logic;
signal A1B2 : std_logic;
signal A2B2 : std_logic;
signal A3B2 : std_logic;
signal A4B2 : std_logic;
signal A5B2 : std_logic; 
signal A6B2 : std_logic;
signal A7B2 : std_logic;

signal A0B3 : std_logic;
signal A1B3 : std_logic;
signal A2B3 : std_logic;
signal A3B3 : std_logic;
signal A4B3 : std_logic;
signal A5B3 : std_logic; 
signal A6B3 : std_logic;
signal A7B3 : std_logic;

signal A0B4 : std_logic;
signal A1B4 : std_logic;
signal A2B4 : std_logic;
signal A3B4 : std_logic;
signal A4B4 : std_logic;
signal A5B4 : std_logic; 
signal A6B4 : std_logic;
signal A7B4 : std_logic;

signal A0B5 : std_logic;
signal A1B5 : std_logic;
signal A2B5 : std_logic;
signal A3B5 : std_logic;
signal A4B5 : std_logic;
signal A5B5 : std_logic; 
signal A6B5 : std_logic;
signal A7B5 : std_logic;

signal A0B6 : std_logic;
signal A1B6 : std_logic;
signal A2B6 : std_logic;
signal A3B6 : std_logic;
signal A4B6 : std_logic;
signal A5B6 : std_logic; 
signal A6B6 : std_logic;
signal A7B6 : std_logic;

signal A0B7 : std_logic;
signal A1B7 : std_logic;
signal A2B7 : std_logic;
signal A3B7 : std_logic;
signal A4B7 : std_logic;
signal A5B7 : std_logic; 
signal A6B7 : std_logic;
signal A7B7 : std_logic;
 
 
 
begin
 
 
A1B0 <= A(1) and B(0);
A2B0 <= A(2) and B(0);
A3B0 <= A(3) and B(0);
A4B0 <= A(4) and B(0);
A5B0 <= A(5) and B(0);
A6B0 <= A(6) and B(0);
A7B0 <= A(7) and B(0);

A0B1 <= A(0) and B(1);
A1B1 <= A(1) and B(1);
A2B1 <= A(2) and B(1);
A3B1 <= A(3) and B(1);
A4B1 <= A(4) and B(1);
A5B1 <= A(5) and B(1);
A6B1 <= A(6) and B(1);
A7B1 <= A(7) and B(1);

A0B2 <= A(0) and B(2);
A1B2 <= A(1) and B(2);
A2B2 <= A(2) and B(2);
A3B2 <= A(3) and B(2);
A4B2 <= A(4) and B(2);
A5B2 <= A(5) and B(2);
A6B2 <= A(6) and B(2);
A7B2 <= A(7) and B(2);

A0B3 <= A(0) and B(3);
A1B3 <= A(1) and B(3);
A2B3 <= A(2) and B(3);
A3B3 <= A(3) and B(3);
A4B3 <= A(4) and B(3);
A5B3 <= A(5) and B(3);
A6B3 <= A(6) and B(3);
A7B3 <= A(7) and B(3);

A0B4 <= A(0) and B(4);
A1B4 <= A(1) and B(4);
A2B4 <= A(2) and B(4);
A3B4 <= A(3) and B(4);
A4B4 <= A(4) and B(4);
A5B4 <= A(5) and B(4);
A6B4 <= A(6) and B(4);
A7B4 <= A(7) and B(4);

A0B5 <= A(0) and B(5);
A1B5 <= A(1) and B(5);
A2B5 <= A(2) and B(5);
A3B5 <= A(3) and B(5);
A4B5 <= A(4) and B(5);
A5B5 <= A(5) and B(5);
A6B5 <= A(6) and B(5);
A7B5 <= A(7) and B(5);

A0B6 <= A(0) and B(6);
A1B6 <= A(1) and B(6);
A2B6 <= A(2) and B(6);
A3B6 <= A(3) and B(6);
A4B6 <= A(4) and B(6);
A5B6 <= A(5) and B(6);
A6B6 <= A(6) and B(6);
A7B6 <= A(7) and B(6);

A0B7 <= A(0) and B(7);
A1B7 <= A(1) and B(7);
A2B7 <= A(2) and B(7);
A3B7 <= A(3) and B(7);
A4B7 <= A(4) and B(7);
A5B7 <= A(5) and B(7);
A6B7 <= A(6) and B(7);
A7B7 <= A(7) and B(7);
 
 
--first stage
 
P0          : P(0) <= A(0) and B(0) ;
 
ha11 : Halfaddar port map(A=>A1B0,B=>A0B1,S=>P(1),Cout=>C1);
fa12 : Full_Addar port map(A=>A2B0,B=>A1B1,Cin=>A0B2,S=>S2,Cout=>C2);
fa13 : Full_Addar port map(A=>A3B0,B=>A2B1,Cin=>A1B2,S=>S3,Cout=>C3);
fa14 : Full_Addar port map(A=>A4B0,B=>A3B1,Cin=>A2B2,S=>S4,Cout=>C4);
fa15 : Full_Addar port map(A=>A5B0,B=>A4B1,Cin=>A3B2,S=>S5,Cout=>C5);
fa16 : Full_Addar port map(A=>A6B0,B=>A5B1,Cin=>A4B2,S=>S6,Cout=>C6);
fa17 : Full_Addar port map(A=>A7B0,B=>A6B1,Cin=>A5B2,S=>S7,Cout=>C7);
ha18 : Halfaddar port map(A=>A7B1,B=>A6B2,S=>S8,Cout=>C8);

-- Second stage
ha21 : Halfaddar port map(A=>S2,B=>C1,S=>P(2),Cout=>C9);
fa22 : Full_Addar port map(A=>S3,B=>C2,Cin=>A0B3,S=>S10,Cout=>C10);
fa23 : Full_Addar port map(A=>S4,B=>C3,Cin=>A1B3,S=>S11,Cout=>C11);
fa24 : Full_Addar port map(A=>S5,B=>C4,Cin=>A2B3,S=>S12,Cout=>C12);
fa25 : Full_Addar port map(A=>S6,B=>C5,Cin=>A3B3,S=>S13,Cout=>C13);
fa26 : Full_Addar port map(A=>S7,B=>C6,Cin=>A4B3,S=>S14,Cout=>C14);
fa27 : Full_Addar port map(A=>S8,B=>C7,Cin=>A5B3,S=>S15,Cout=>C15);
fa28 : Full_Addar port map(A=>A7B2,B=>C8,Cin=>A6B3,S=>S16,Cout=>C16);

-- Third stage
ha31 : Halfaddar port map(A=>S10,B=>C9,S=>P(3),Cout=>C17);
fa32 : Full_Addar port map(A=>S11,B=>C10,Cin=>A0B4,S=>S18,Cout=>C18);
fa33 : Full_Addar port map(A=>S12,B=>C11,Cin=>A1B4,S=>S19,Cout=>C19);
fa34 : Full_Addar port map(A=>S13,B=>C12,Cin=>A2B4,S=>S20,Cout=>C20);
fa35 : Full_Addar port map(A=>S14,B=>C13,Cin=>A3B4,S=>S21,Cout=>C21);
fa36 : Full_Addar port map(A=>S15,B=>C14,Cin=>A4B4,S=>S22,Cout=>C22);
fa37 : Full_Addar port map(A=>S16,B=>C15,Cin=>A5B4,S=>S23,Cout=>C23);
fa38 : Full_Addar port map(A=>A7B3,B=>C16,Cin=>A6B4,S=>S24,Cout=>C24);

-- fourth stage
ha41 : Halfaddar port map(A=>S18,B=>C17,S=>P(4),Cout=>C25);
fa42 : Full_Addar port map(A=>S19,B=>C18,Cin=>A0B5,S=>S26,Cout=>C26);
fa43 : Full_Addar port map(A=>S20,B=>C19,Cin=>A1B5,S=>S27,Cout=>C27);
fa44 : Full_Addar port map(A=>S21,B=>C20,Cin=>A2B5,S=>S28,Cout=>C28);
fa45 : Full_Addar port map(A=>S22,B=>C21,Cin=>A3B5,S=>S29,Cout=>C29);
fa46 : Full_Addar port map(A=>S23,B=>C22,Cin=>A4B5,S=>S30,Cout=>C30);
fa47 : Full_Addar port map(A=>S24,B=>C23,Cin=>A5B5,S=>S31,Cout=>C31);
fa48 : Full_Addar port map(A=>A7B4,B=>C24,Cin=>A6B5,S=>S32,Cout=>C32);

-- Fifth Stage
ha51 : Halfaddar port map(A=>S26,B=>C25,S=>P(5),Cout=>C33);
fa52 : Full_Addar port map(A=>S27,B=>C26,Cin=>A0B6,S=>S34,Cout=>C34);
fa53 : Full_Addar port map(A=>S28,B=>C27,Cin=>A1B6,S=>S35,Cout=>C35);
fa54 : Full_Addar port map(A=>S29,B=>C28,Cin=>A2B6,S=>S36,Cout=>C36);
fa55 : Full_Addar port map(A=>S30,B=>C29,Cin=>A3B6,S=>S37,Cout=>C37);
fa56 : Full_Addar port map(A=>S31,B=>C30,Cin=>A4B6,S=>S38,Cout=>C38);
fa57 : Full_Addar port map(A=>S32,B=>C31,Cin=>A5B6,S=>S39,Cout=>C39);
fa58 : Full_Addar port map(A=>A7B5,B=>C32,Cin=>A6B6,S=>S40,Cout=>C40);

-- Sixth Stage 
ha61 : Halfaddar port map(A=>S34,B=>C33,S=>P(6),Cout=>C41);
fa62 : Full_Addar port map(A=>S35,B=>C34,Cin=>A0B7,S=>S42,Cout=>C42);
fa63 : Full_Addar port map(A=>S36,B=>C35,Cin=>A1B7,S=>S43,Cout=>C43);
fa64 : Full_Addar port map(A=>S37,B=>C36,Cin=>A2B7,S=>S44,Cout=>C44);
fa65 : Full_Addar port map(A=>S38,B=>C37,Cin=>A3B7,S=>S45,Cout=>C45);
fa66 : Full_Addar port map(A=>S39,B=>C38,Cin=>A4B7,S=>S46,Cout=>C46);
fa67 : Full_Addar port map(A=>S40,B=>C39,Cin=>A5B7,S=>S47,Cout=>C47);
fa68 : Full_Addar port map(A=>A7B6,B=>C40,Cin=>A6B7,S=>S48,Cout=>C48);

--Seventh Stage 
ha71 : Halfaddar port map(A=>S42,B=>C41,S=>P(7),Cout=>C49);
fa72 : Full_Addar port map(A=>S43,B=>C42,Cin=>C49,S=>P(8),Cout=>C50);
fa73 : Full_Addar port map(A=>S44,B=>C43,Cin=>C50,S=>P(9),Cout=>C51);
fa74 : Full_Addar port map(A=>S45,B=>C44,Cin=>C51,S=>P(10),Cout=>C52);
fa75 : Full_Addar port map(A=>S46,B=>C45,Cin=>C52,S=>P(11),Cout=>C53);
fa76 : Full_Addar port map(A=>S47,B=>C46,Cin=>C53,S=>P(12),Cout=>C54);
fa77 : Full_Addar port map(A=>S48,B=>C47,Cin=>C54,S=>P(13),Cout=>C55);
fa78 : Full_Addar port map(A=>A7B7,B=>C48,Cin=>C55,S=>P(14),Cout=>P(15));


end Behavioral;
